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Jobs and careers temporary for senior verification engineer in Santa Clara (2 jobs)

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Design Verification Engineer with UVM,OVM, SystemVerilog & Python

  • PDDN Inc
  • Santa Clara
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... /C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and ... Universal verification methodology-UVM IPs and ...
27 days ago

Principal Systems Engineer

  • Estuate Inc.
  • Santa Clara
Description: Principal Systems Engineer Santa Clara, CA Contract W2 ... generation sequencing technology. The Principal/Senior System Engineer s focus is on improving ...
17 hours ago

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