Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
16 days ago
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
17 days ago
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
24 days ago
... PythonProficient in using industry-standard design software, including Cadence Virtuoso, ... Calibre DRC, LVS toolsExperience supporting design teams working with analog and ... digital design flowsExcellent communication skills and ability ...
12 days ago
... Description: Job Title FPGA RTL design and Board validation ... seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... in RTL design, IP design and development, and FPGA validation and ... have a strong background in design debugging and a deep ...
18 days ago
... Description: Job Title FPGA RTL design and Board validation ... seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... in RTL design, IP design and development, and FPGA validation and ... have a strong background in design debugging and a deep ...
18 days ago
... Description: Job Title FPGA RTL design and Board validation ... seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... in RTL design, IP design and development, and FPGA validation and ... have a strong background in design debugging and a deep ...
19 days ago
... Description: Job Title FPGA RTL design and Board validation ... seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... in RTL design, IP design and development, and FPGA validation and ... have a strong background in design debugging and a deep ...
22 days ago
... looking for a AI Engineer for our client in Santa ... CA Job Title: AI Engineer Job Location: Santa Clara ... - $65hrThe Generative AI Design Engineer will design, develop, and optimize generative ... as content creation, product design, intelligent automation, and ...
4 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
5 days ago
Description: Title: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA-Onsite ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop forward ...
8 days ago
... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
8 days ago
... are looking for DFT / ATPG Engineer for our client in Santa ... , CA Job Title: DFT / ATPG Engineer Job Location: Santa Clara, CA ... : Pay Range: $82hr - $103hrThe DFT Design Engineer will be part of the ... DFT design team responsible for scan/ATPG ...
25 days ago
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... methodologies.Strong knowledge of FPGA, ASIC, and RTL design.Hands-on experience ...
28 days ago
Description: Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
28 days ago
Description: Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
29 days ago
... Title: Materials Science AI Engineer Job Location: Santa Clara, ... Range: $60hr - $65hrResponsibilities: Design, develop and deploy multi-modal ... solve material physics and design problems.Aggregate, process, ... modeling and analysis.Design, develop and maintain ...
3 days ago
... , We are looking for SOC Design Verification Engineer, and the following below ... updated resume. Role: SOC Design Verification Engineer Work location: Santa Clara, CA ...
26 days ago
... . The Hardware Engineer team works closely to define, design and integrate the ... and systems. As a Hardware Validation Engineer, you will gain expertise using ... latest leading edge server designs. Our systems are designed in house using ...
an hour ago
Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... using SystemVerilog and UVM. The engineer will own verification of complex ...
3 days ago