Description:
Looking for Lead layout design for high-performance analog cores (ADCs, DACs, PLLs, transceivers) in CMOS process nodes (5nm to 65nm). Set up LVS, DRC, and ERC environments, debug using Cadence and Mentor tools. Perform floor planning, routing, and chip assembly. Apply advanced analog layout techniques (e.g., common centroid, shielding, thermal-aware layout). Ensure high-performance analog layout for mass production, including FinFET process nodes. : 10+ years of experience in high-performance a
Feb 14, 2025;
from:
dice.com