Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
28 days ago
Description: Title:- Board Level Test Engineer Location:- Santa Clara, CA Key ... methodologies. Develop and maintain test automation using Shell and Python scripting ...
13 days ago
... are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ...
22 days ago
... are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ...
22 days ago
... are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ...
23 days ago
... are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years ...
26 days ago