Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... analog mixed-signal interfaces. Develop test plans and coverage metrics from ... writing block and chip-level tests. Creat
4 days ago
Description: Role: DFT Engineer Location: Santa Clara, CA Interview: ... -on experience with DFT and test flow with commercial EDA tools ... DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic ...
24 days ago