Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... /C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and ... Universal verification methodology-UVM IPs and ...
3 days ago
... & Skill Requirement: 5- 10yrs Exp range engineers Required Port schematics from the ... and present Pre-Layout Design Review Guide layout engineer to implement the ... design targets Prepare and present Post-Layout Design Review Complete all necessary verification ...
13 hours ago
... Signal Integrity Engineer focusing on SI, PI design, and verification located in Santa ... a diverse group of highly motivated engineers who are passionate about designing ...
3 days ago
Description: As a Project Design Engineer, you will be a key member ...
5 days ago
... automation to prevent problem recurrence. Design, write, and deploy software to ... Oracle products and services. Design and develop designs, architectures, standards, and methods ...
3 days ago
Description: Data Engineer role with PM skills Santa ... expertise in data modeling, ETL design, and data integrationStrong understanding of ...
2 days ago
... embedded software development and system design 3+ years of experience in SW ...
19 hours ago
... . 3+ years of experience in software design and coding of Layer2/L3 ...
19 hours ago