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Jobs and careers for fpga verification engineer in Santa Clara (3 jobs)

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Design Verification Engineer with UVM,OVM, SystemVerilog & Python

  • PDDN Inc
  • Santa Clara
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... /C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and ... Universal verification methodology-UVM IPs and ...
5 days ago

Analog Layout Engineer

  • Intellectt INC
  • Santa Clara
Description: Analog Layout Engineer Location: Santa Clara, CA ... Skill Requirement: 5- 10yrs Exp range engineers Required Port schematics from the ... Design Review Guide layout engineer to implement the layout ... Review Complete all necessary verification checks and
a day ago

Staff Signal Integrity Engineer

  • Johnson & Johnson
  • Santa Clara
... Signal Integrity Engineer focusing on SI, PI design, and verification located in ... a diverse group of highly motivated engineers who are passionate about designing ...
4 days ago
Analog Layout Engineer Staff Signal Integrity Engineer

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