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Functional tester
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Jobs and careers for functional tester in Santa Clara
(1 jobs)
Lead fpga verification engineer with uvm /verilog system-active requirement
dice.com
Company
Data Capital Inc
(
+1
)
Schedule
Full-day
(
+1
)
Employment
Full-time
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+1
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Location
Santa Clara
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement
Data Capital Inc
Santa Clara
... VCS) Experience with code and
functional
coverage analysis Proficient in debugging ...
a month ago
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