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Seniorrtl design engineer
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Jobs and careers for seniorrtl design engineer in Santa Clara
(1 jobs)
Design verification engineer with uvm,ovm, systemverilog & python
Company
PDDN Inc
(
+1
)
Period
Last month
(
+1
)
Schedule
Full-day
(
+1
)
Employment
Temporary
(
+1
)
Source
dice.com
(
+1
)
Location
Santa Clara
(
+1
)
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Design
Verification
Engineer
with UVM,OVM, SystemVerilog & Python
PDDN Inc
Santa Clara
Description: Role:
Design
Verification
Engineer
Location: Santa Clara, CA Interview: ...
19 days ago
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