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Jobs and careers for soc design verification engineer in Santa Clara (2 jobs)

Senior fpga engineer
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Senior FPGA Engineer

  • Data Capital Inc
  • Santa Clara
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
a day ago

Senior FPGA Engineer

  • Data Capital Inc
  • Santa Clara
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
2 days ago

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