Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... /C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and ... Universal verification methodology-UVM IPs and ...
4 days ago
... : Silicon Design Engineer - Onsite Description: SENIOR SILICON DESIGN ENGINEER THE ROLE: This ... , Place n Route, timing, and Physical Verification THE PERSON: Strong communication skills ... spread-out teams RESPONSIBILTIES: This engineer will work on high-speed ...
8 days ago