Description: Role: Design Verification Engineer Location: Santa Clara, CA ... Create verification environments using System-Verilog and Universal verification ... mixed-signal interfaces. Develop test plans and coverage metrics ... block and chip-level tests. Creat
6 days ago
Description: Role: DFT Engineer Location: Santa Clara, CA Interview: ... -on experience with DFT and test flow with commercial EDA tools ... DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic ...
26 days ago
... are looking for a SAN Storage Engineer - Location: Santa Clara, CA ... Position. Job Title: SAN Storage Engineer Employment Type: Contract 9 months ... looking for a Senior level SAN/Storage engineer responsible for storage ... diverse enterprise storage systems. Inc
19 days ago