... : Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead II ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... will work closely with design engineers to develop and execute verification pla
24 days ago
... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in ... Skill 2 5 +Years of Exp in System Verlilog Job Description: Strong understanding ... in System Verilog and UVM verification methodology. Experience with industry-standard verification ...
23 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
a month ago
... principles and architecturesProficiency in System Verilog and UVM verification methodologyExperience with Linux ... operating systemExperience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps ...
9 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
19 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
26 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
27 days ago
... a highly skilled IT Google Workspace Engineer to join our client s onsite ... expert in Google Workspace administration, system engineering, automation, and enterprise-level ...
20 days ago
... -on experience with the queuing system such as RabbitMQ, Kafka, experience ...
27 days ago
... Language 2. Hands on experience with System Verilog 3. Knowledge in AI ML ... Developer experience Technologies: C++ Programming Language System Verilog ASIC Required Education: . Bachelors ...
10 days ago
... intricate technical problems across various systems and platforms. Proficient in utilizing ...
13 days ago
... -throughput, and highly available storage systems across 1
17 days ago
... IdPs (specifically Okta) and MFA systems. Scripting: Ability to replace legacy ...
19 days ago
... 's degree in Computer Science, Information Systems, Software Engineering, Electrical/Electronics Engineering ...
23 days ago
Description: 3-5 Years experience in system level testing of datacenter products ...
27 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
2 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
3 days ago
Description: Job Title: ASIC Engineer Location: Santa Clara, CA, 95051 ... specifications, logic designs, and/or system simulations based on ...
4 days ago
... : Job Title: Google Workspace Admin/Engineer Location: Santa Clara, CA- (Hybrid ... Role Overview As a Google Workspace Engineer, you will manage and optimize ... pivotal in supporting enterprise IT systems, driving automation, and collaborating with ...
6 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ... -based platform seamlessly connects people, systems, and processes to empower organizations ...
7 days ago