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Jobs and careers temporary for systems engineer from the company Pddn inc in Santa Clara (2 jobs)

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Pddn inc
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Design Verification Engineer with UVM,OVM, SystemVerilog & Python

  • PDDN Inc
  • Santa Clara
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... and Create verification environments using System-Verilog and Universal verification methodology ...
5 days ago

DFT Engineer

  • PDDN Inc
  • Santa Clara
Description: Role: DFT Engineer Location: Santa Clara, CA Interview: ...
25 days ago

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