Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... and Create verification environments using System-Verilog and Universal verification methodology ... mixed-signal interfaces. Develop test plans and coverage metrics from ...
4 hours ago
Description: Role: DFT Engineer Location: Santa Clara, CA Interview: ... -on experience with DFT and test flow with commercial EDA tools ... DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic ...
19 days ago