... : ASIC Engineer (Design Verification ... test benches to enable IP/sub-system/SoC level verification. Develop functional tests ... based on verification test ... verification metrics on test plan, functional ...
14 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... GDSII) - Experience with SoC level integration (multiple blocks, SoC floorplan, clocking ...
14 days ago