Description: ASIC Engineer (Design Verification) Bay Area, CA ... implement IP/SoC verification plans, build verification test benches to ... sub-system/SoC level verification. Develop functional tests ... based on verification test plan. Drive Design Verification to ...
18 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... experience performing timing and physical verification closure on 5nm FinFET TSMC ...
18 days ago
Description: Skills Required Selenium- 5-10 Years Selenium WebDriver- 5-10 Years UI Automation- 5-10 Years WebApp UI Automation - 5-10 Years Generative AI - At least 1 year Functional Testing - 5-10 Years Java - 5-10 Years
29 days ago