Description: ASIC Engineer (Design Verification) Bay Area, CA ... implement IP/SoC verification plans, build verification test benches to ... sub-system/SoC level verification. Develop functional tests ... based on verification test plan. Drive Design Verification to ...
7 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... experience performing timing and physical verification closure on 5nm FinFET TSMC ...
7 days ago