Description: ASIC Engineer (Design Verification) Bay Area ... verification plans, build verification test benches to enable IP ... . Develop functional tests based on verification test plan. Drive ... defined verification metrics on test plan, functional and code ...
20 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... GDSII) - Experience with SoC level integration (multiple blocks, SoC floorplan, clocking ...
20 days ago