Description: 3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one ...
2 days ago
Description: You will be an Executive Assistant to two Sr Directors. Daily activities will include challenging calendar management, coordinate meetings and video/conference calls while actively utilizing your keen problem-solving abilities as challenges ...
18 days ago
Description: Key Responsibilities: Collaborate with business stakeholders to gather and refine requirements, ensuring alignment with technical feasibility and system design.Work closely with cross-functional teams, including developers, product managers, ...
22 days ago