Where

Design Verification Engineer

Veear
Sunnyvale Full-day Temporary

Description:

3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.Experience in architecting and im
Oct 1, 2025;   from: dice.com

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