Description:
Job Responsibilities: Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVMDevelop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functionsCollect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;Enhance your leadership skills while contributing to a dynamic DV teamCreate reusable Verification IP
Oct 6, 2025;
from:
dice.com