... with technical feasibility and system design.Work closely with cross-functional ... blockers.Actively participate in the design, development, testing, and deployment of ...
22 days ago
Description: 3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one ...
2 days ago