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Jobs and careers for design verification engineer from the company Veear in Sunnyvale (2 jobs)

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Design Verification Engineer

  • Veear
  • Sunnyvale
... in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience ... following areas along with functional verification - SV Assertions, Formal, Emulation ... tools and flows for verification environments.Experience in architecting ...
28 days ago

Sr. Network Engineer

  • Veear
  • Sunnyvale
... guidance and support for the design, deployment, and management of Cisco ...
15 days ago

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