... experienced ASIC Power Engineer to support power analysis and optimization for next ... power, performance, and area (PPA) optimization across RTL and netlist levels ...
13 days ago
Description: Role: ASIC Power Engineer Location: Sunnyvale, CA (Hybrid) DUTIES: ... ASIC Power Engineer to perform power analysis and optimizations in ASIC for ... and SystemVerilog. RESPONSIBILITIES: Perform PPA optimization with Fusion compiler. Perform RTL ...
13 days ago
... Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ... and SystemVerilog. RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL ...
13 days ago
... , scalability, and reliability, addressing query optimization and caching strategies Partner closely ...
10 days ago