... experienced ASIC Power Engineer to support power analysis and optimization for next ... power, performance, and area (PPA) optimization across RTL and netlist levels ...
2 days ago
Description: Role: ASIC Power Engineer Location: Sunnyvale, CA (Hybrid) DUTIES: ... ASIC Power Engineer to perform power analysis and optimizations in ASIC for ... and SystemVerilog. RESPONSIBILITIES: Perform PPA optimization with Fusion compiler. Perform RTL ...
2 days ago
... Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ... and SystemVerilog. RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL ...
2 days ago