Description: Job Title: Design Verification Engineer Location: Sunnyvale CA /Redmond WA/ ... Verilog-based verification environments for IP/subsystem/SoC level testing Develop ...
2 days ago
... verbal communication skills. Communicating with engineers is a part of the job ... us to dig into TCP/IP, the DNS spec, logging infrastructure ...
a day ago
... verbal communication skills. Communicating with engineers is a part of the job ... us to dig into TCP/IP, the DNS spec, Walmart's logging ...
a day ago