Description:
Job Title: Design Verification Engineer Location: Sunnyvale CA /Redmond WA/ Austin TX(Hybrid) Duration: Full-Time Only Job Description:- Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and clos
May 21, 2025;
from:
dice.com