Description: Pre-Silicon Verification Engineer Contract @ CA & TX - Onsite Job ... in Verilog, System Verilog, C/C++ based verification, and UVM methodologyExperience i
5 days ago
Description: Title: Post Silicon Engineer Location: Sunnyvale CA- Onsite Position ... 's/DSP) in Pre-Silicon (Virtual, Emulation and fpga platforms) & Post-Silicon (
7 days ago
Description: Title: Post Silicon Engineer Location: Sunnyvale, CA Type: Contract ... s/DSP) in Pre-Silicon (Virtual, Emulation and fpga platforms) & Post-Silicon ...
8 days ago
Description: ASIC Engineer (Design Verification) Bay Area, CA ... implement IP/SoC verification plans, build verification test benches to ... sub-system/SoC level verification. Develop functional tests ... based on verification test plan. Drive Design Verification to ...
7 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... experience performing timing and physical verification closure on 5nm FinFET TSMC ...
7 days ago
... : Position : STA (Static Timing Analysis) Engineer Location: Sunnyvale CA or Redmond ... role Static Timing Analysis (STA) Engineer (NO 15+ YEARS RESUME) Job ... Analysis (STA) Engineer to contribute to the timing verification and closure of ...
21 days ago