Description: Pre-Silicon Verification Engineer Contract @ CA & TX - Onsite Job ... in Verilog, System Verilog, C/C++ based verification, and UVM methodologyExperience i
22 days ago
Description: ASIC Engineer (Design Verification) Bay Area, CA ... implement IP/SoC verification plans, build verification test benches to ... sub-system/SoC level verification. Develop functional tests ... based on verification test plan. Drive Design Verification to ...
24 days ago
Description: Position: Principal Data Engineer Location: Onsite 2 days a week in ... : 6 month contract to hire - W2 Iv Process: Two steps both with ... engineering team of 10-20 engineers driving technical excellence through architectu
10 days ago
... : Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin ... experience performing timing and physical verification closure on 5nm FinFET TSMC ...
24 days ago