... experienced ASIC Power Engineer to support power analysis and optimization for next ... ) optimization across RTL and netlist levels, working closely with synthesis, physical design ...
13 days ago
Description: Role: ASIC Power Engineer Location: Sunnyvale, CA (Hybrid) DUTIES: ... ASIC Power Engineer to perform power analysis and optimizations in ASIC for ... and SystemVerilog. RESPONSIBILITIES: Perform PPA optimization with Fusion compiler. Perform RTL ...
13 days ago