Description:
Required: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements specifications Experience developing designs from scratch Experience applying linting and other (QC) quality checking and basic verification of designs. Experience supporting SoC designers in integration as needed Strong communication and collaboration skills Preferred: -Desirable but not essential experience: DMA, me
Feb 17, 2025;
from:
dice.com