Pre-Silicon Verification Engineer (System Verilog and UVM)

Description:

Title: Pre-Silicon Verification Engineer Contract Length: Initial 6-month contract (potential to go 18-months) Location:100% onsite in either Sunnyvale, CA, San Francisco, CA or Austin TX Minimum Requirements Ideal range is 10-15 years: However, they are open to candidates with 7-20 years of experienceSemiconductor background is a mustExperience in the semiconductor industry is essential.The focus is on System Verilog and UVM expertiseHands-on experience in Verilog, System Verilog, C/C++ based