Description:
Position: Senior Design Verification Engineer Location: Mountainview, California (Complete onsite) Experience: 7 to 12 years only (Relevant) What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is mustAt-least 5+ years of experience in System Verilog HVL and C/C++.AMBA AXI bus along-with ARM or C based processorBi-frost/Processor based C and SV/UVM mix Verification. What we are looking for: A bachelor s degree in electrical or computer engineering, accompanied by a mi
May 10, 2025;
from:
dice.com