Description:
Hi, Hope you are doing good Position: Senior Design Verification Engineer Location: Mountainview, California (Complete onsite) locals preferred Duration: 6-12 months Interview: video Experience: 7 to 12 years only (Relevant) What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Bi-frost/Processor based C and SV/UVM mix Verification. What we
May 21, 2025;
from:
dice.com