Where

Senior ASIC/RTL Design Engineer

Cynet Systems
San Jose Full-day Temporary

Description:

Job Description: Pay Range: $74.78hr - $78.78hr Responsibilities: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. CollaboXX with architecture and hardware teams to understand the requirements. Work with verification and physical design teams to achieve high quality design and successful tape out. XXgn and implement logic functions that enable efficient test and debug. Participate in
May 29, 2025;   from: dice.com

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