Description:
Job Description: Pay Range: $82hr - $103hr This is a position for a senior level RTL design engineer. As a part of the design team, candidates will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes. This DFX RTL XXgn Engineer is expected to contribute in : Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into
Jun 4, 2025;
from:
dice.com