Description:
Title: Analog Layout Engineer. Location: Santa Clara, CA. Duration: 12+ Months Contract Position. Description: The ideal candidate should have a minimum of BS/MS in Electrical Engineering with 8+ years of experience in high-speed/precision Analog layout designs in deep Sub-Micron process technologies (FinFET). Experience in industry standard Mask Design/Verification Tools (Cadence/Synopsys, Calibre)Hands-on custom layout design experience of high-speed SerDes blocks like Equalizers, PLL, Phase
Jul 9, 2025;
from:
dice.com