Description:
Position: Analog Layout Design Engineer Location: Santa Clara, CA Contract Type: 3-Month Contract-to-Hire Responsibilities: Perform layout of cutting-edge, high-performance, high-speed CMOS ICs in mature foundry nodes (40nm, 55nm, 65nm, 130nm).Collaborate with circuit designers to review and analyze floorplans and complex circuits.Run full sets of design verification tools for AMS blocks.Interpret LVS, DRC, and ERC reports to expedite layout closure.Use advanced CAD tools and mask design experti
Jul 11, 2025;
from:
dice.com