Description:
Position: PSV DDR Validation EngineerLocation: San Jose, CARate: Case to case basisExperience: 10-15 yearsEducation: B.E/M. E in Electronics & Communication EngineeringTake lead responsibility for validating DDR memory subsystems (LPDDR4x, LPDDR5x) on multiple SoC platforms.Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability.Collaborate with design and firmware teams to de
Aug 13, 2025;
from:
dice.com