Description:
7+ years of experience in RTL synthesis and physical implementation using Synopsys tools (Fusion Compiler, Design Compiler, PrimeTime). Strong command of RTLA and PrimePower RTL flows, including switching activity modeling and scenario-based analysis. Proficiency in scripting (TCL, Python) for flow automation and debugging. Deep understanding of timing constraints, UPF, and low-power design methodologies. Experience with Linux and bash scripting skills are preferred. Familiarity with advanced pr
Aug 27, 2025;
from:
dice.com