Description:
About the RoleWe are seeking an experienced Formal Verification Engineer with strong expertise in FPV, DPV, AEP & SEQ setups and SystemVerilog Assertions to join our dynamic verification team. This role offers the opportunity to work on complex verification environments and contribute directly to ensuring design correctness and product quality. Location: San Jose or Austin TX Key Responsibilities Develop and maintain formal verification setups using SystemVerilog modules and assertions. Execute
Oct 1, 2025;
from:
dice.com