Description:
Role: FPGA Verification Engineer Location: Santa Clara, CA (Onsite from Day 1) Contract Must Have Skills: FPGA Verification Engineer Skill 1 8 + Years of in FPGA Skill 2 5 +Years of Exp in UVM Skill 2 5 +Years of Exp in System Verlilog Key Responsibilities: Develop and execute comprehensive verification plans for FPGA designs. Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog). Write and debug test cases to verify functionality, perf
Oct 16, 2025;
from:
dice.com