Description:
Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and debug test cases for functional and performance validation.Identify and resolve design issues in collaboration with engineering teams.Participate in design reviews and contribute to verification strategy.Stay current with the latest verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog, UVM, and tools like QuestaSim, VCS, or Haps.Familiar with
Oct 29, 2025;
from:
dice.com