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Package designer (IC package design and development / Cadence Allegro Package Designer )

Wise Equation Solutions Inc.
San Jose Full-day Temporary

Description:

Location: San Jose, CA and Phoenix, AZ ( Onsite) 3 to 8+ years in IC package design and development. Proficiency with Cadence Allegro Package Designer. Experience in Wire bond, Flip chip Substrate designs. Hands on experience with Wire bond, Flip chip & advanced packaging technologies (2.5D, 3D, RDL, embedded passives, etc.) Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWoS. Knowledge of different OSAT design rule
Oct 31, 2025;   from: dice.com
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