Senior SystemVerilog Verification Engineer with FPGA

Description:

Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) Experience with code and functional coverage analysis Proficient in debugging and problem-solving Scripting experience in Python or Perl Knowledge of Verilog and/or VHDL