Description:
Job Title: RTL / FPGA Design EngineerLocation: San Jose, CA(Onsite)Duration: Contract(W2 Only) Job Summary:We are seeking an experienced RTL / FPGA Design Engineer with strong hands-on expertise in FPGA design, simulation, synthesis, and implementation. The ideal candidate will have solid experience using Vivado, along with TCL and Python scripting, and will contribute across the full product development lifecycle. Key Responsibilities:Design, develop, and maintain RTL code using Verilog/SystemV
Feb 3, 2026;
from:
dice.com