... testing, failure debug, gate level simulations, assertions, and coverage closure.
9 days ago
... testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient ...
26 days ago
Description: Hands-on experience in the design of semiconductor packages, multi-chip modules and PCB's using tool suites from Mentor and Cadence. Understanding of semiconductor packaging technology like wire bond, flip chip and wafer level packaging. ...
13 days ago
Description: - 5+ years' experience in lab setup, management and improvement - 5+ years of hands-on lab technician experience - Working experience with embedded HW is a must - Experience with Linux CLI is a must - Use engineering test setup, data ...
16 days ago