Description: Role: PCIe Verification Engineer Position Type: Contract Location: San ... the pre-silicon verification of next-generation PCIe Switch and Retimer designs ...
a day ago
Description: Position: PCIe Validation Engineer Experience: 5 8 Years Location : San ... Python, Lab Tools Role Highlights: PCIe subsystem validation on SoC platformsPost ... and debuggingFirmware integration and PCIe trainingPerformance and reliability testing ...
14 days ago
... Description: Job Title: FPGA Design/Verification Engineer Duration: 6+ Months (Possible Extension) ... & FPGA verification on R&D program. This engineer will be a verification UVM expert. This engineer with ... designs including creating UVM verification environ
22 days ago
Description: Job Title : FPGA Verification Engineer Santa Clara, CA- 5 days onsite ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... closely with design engineers to develop and execute verification plans, identify and ...
7 days ago
... (Hybrid) Project descriptionThe Principal Design Verification Engineer, within the NPU Hardware & ... a broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
... Project Description: The Principal Design Verification Engineer, within the NPU Hardware & ... broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
8 days ago
Description: Job Title: GPU Design Verification Engineer Location: San Jose, CA (Onsite) ... are seeking a highly skilled Design Verification Engineer to join our team at ... be on developing and executing verification plans, creating testbenches, and debugging ...
21 days ago
... are seeking a highly skilled Design Verification Engineer to join our team.The ... be on developing and executing verification plans, creating testbenches, and debugging ... . Responsibilities Develop and execute comprehensive verification plans for GPU
22 days ago
Description: Skill Need: PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
15 days ago
Description: FPGA Verification EngineerMountain View, CA (On-Site) ... Verilog and UVM verification methodologySkill 3 Experience in FPGA verification Good To have ... experience in FPGA design or verification. Familiarity wit
13 days ago
... to build scalable and reusable verification components.Analyze and improve code ... coverage metrics to ensure thorough verification.Write and maintain scripts (e.g., Python ... , Perl, Tcl) to automate verification flows and data
21 days ago
Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
a day ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
6 days ago
Description: Position: Principal Engineer, Design Verification (NPU) Location: Mountain View ... Project description The Principal Design Verification Engineer, within the NPU Hardware ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
Description: Title: Principal Engineer, Design Verification (NPU) Location: Mountain View, ... Project Description: The Principal Design Verification Engineer, within the NPU Hardware & ... experience in AI accelerator verification and automotive safety standards. ...
3 days ago
... Description: Project descriptionThe Principal Design Verification Engineer, within the NPU Hardware & ... broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
a month ago
... IP is hiring for a Verification Engineer to join their high-performance ... team! Responsibilities include: - Developing verification environments using System Verilog and ... UVM - Designing verification components and behavioral models - ...
16 days ago
$85
$90
an hour
Description: SerDes Validation Engineer San Jose, CA (100% Onsite) 6 + ... Have Skills: SerDes HW validation, PCIe & 800G Ethernet, Python, firmware Role ... + 5 yrs experience Strong SerDes validation (PCIe/Ethernet) Python scripting & automation Firmware ...
13 days ago
Description: Job Title: Software Engineer - PCIe Driver Development Location: San Jose, ...
14 days ago