Description: Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ...
6 days ago
... company with expertise in ASIC/FPGA, Analog, and Embedded Software. Headquartered ...
14 days ago
Description: Sr. Hardware Engineer ( Semiconductor ) 12 months contract ... Coverage 5. System Verilog Assertions Design Verification<> JOB DESCRIPTIONGeneral Summary: Join design ... verification team in verifying the high ...
9 days ago
... Job Description As the Senior Engineer in Software Quality Engineering, you ... efforts to deliver quality centric V&V (Verification & Validation) testing Job Description ...
a day ago
Description: Looking for an opportunity to make an impact? At Leidos, we deliver innovative solutions through the efforts of our diverse and talented people who are dedicated to our customers' success. We empower our teams, contribute to our communities, ...
4 days ago